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1 features ?5v 5% write, erase and read ? jedec-standard eeprom commands ? endurance: 10,000 cycles ? fast access time: 100/120/150ns ? fast pagemode access time: 50/60/70ns ? page access depth: 16 bytes/8 words, page address a0, a1, a2 ? sector erase architecture - 16 equal sectors of 128k bytes each - sector erase time: 150ms typical ? auto erase and auto program algorithms - automatically erases any one of the sectors or the whole chip with erase suspend capability - automatically programs and verifies data at specified addresses ? status register feature for detection of program or erase cycle completion p/n: pm0440 rev. 1.6, jul. 16, 1998 ? low vcc write inhibit is equal to or less than 3.2v ? software and hardware data protection ? page program operation - internal address and data latches for 128 bytes/64 words per page - page programming time: 5ms typical - byte programming time: 39us in average ? low power dissipation - 80ma active current - 100ua standby current ? cmos inputs and outputs ? two independently protected sectors ? industry standard surface mount packaging - 44 lead sop general description the MX29F1611 is a 16-mega bit pagemode flash memory organized as either 1m wordx16 or 2m bytex8. the MX29F1611 includes 16-128kb(131,072 bytes) blocks or 16-64kw(65,536 words)blocks. mxic's flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory and fast page mode access. the MX29F1611 is packaged 44-pin sop. it is designed to be reprogrammed and erased in- system or in-standard eprom programmers. the standard MX29F1611 offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. to eliminate bus contention, the MX29F1611 has separate chip enable ce, output enable (oe), and write enable (we) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the MX29F1611 uses a command register to manage this functionality. to allow for simple in-system reprogrammability, the MX29F1611 does not require high input voltages for programming. five-volt-only commands determine the operation of the device. reading data out of the device is similar to reading from an eprom. mxic flash technology reliably stores memory contents even after 10,000 cycles. the mxic's cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the MX29F1611 uses a 5v 5% vcc supply to perform the auto erase and auto program algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc +1v. preliminary MX29F1611 16m-bit [2m x 8/1m x 16] cmos single voltage pagemode flash eeprom
2 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 pin configurations 44 sop(500mil) pin description symbol pin name a0 - a19 address input q0 - q14 data input/output q15/a - 1 q15(word mode)/lsb addr.(byte mode) ce chip enable input oe output enable input we write enable input wp sector write protect input byte word/byte selection input vcc power supply gnd ground pin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 we a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 wp a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc MX29F1611
3 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 block diagram control input logic program/erase high voltage command interface register (cir) MX29F1611 flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 q15/a-1 a0-a19 we oe wp pwd byte pag e write s tat e machine (wsm) y-select
4 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 symbol type name and function a0 - a19 input address inputs: for memory addresses. addresses are internally latched during a write cycle. q0 - q7 input/output low-byte data bus: input data and commands during command interface register(cir) write cycles. outputs array,status and identifier data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. q8 - q14 input/output high-byte data bus: inputs data during x 16 data-write operations. outputs array, identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected or the outputs are disabled . q15/a -1 input/output selects between high-byte data input/output(byte = high) and lsb address(byte = low) ce input chip enable inputs: activate the device's control logic, input buffers, decoders and sense amplifiers. with ce high, the device is deselected and power consumption reduces to standby level upon completion of any current program or erase operations. ce must be low to select the device. oe input output enables: gates the device's data through the output buffers during a read cycle oe is active low. we input write enable: controls writes to the command interface register(cir). we is active low. wp input write protect: top or bottom sector can be protected by writing a non- volatile protect-bit for each sector. when wp is high, all sectors can be programmed or erased regardless of the state of the protect-bits. the wp input buffer is disabled when pwd transitions low(deep power-down mode). byte input byte enable: byte low places device in x8 mode. all data is then input or output on q0-7 and q8-14 float. addressq15/a-1 selects between the high and low byte. byte high places the device in x16 mode, and turns off the q15/a-1 input buffer. address a0, then becomes the lowest order address. vcc device power supply(5v 5%) gnd ground table1.pin descriptions
5 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 mode notes ce oe we a0 a1 a9 q0-q7 q8-q14 q15/a-1 read 1 vil vil vih x x x dout dout vil/vih output disable 1 vil vih vih x x x high z high zx standby 1 vih x x x x x high z high zx deep power-down 1 x x x x x x high z high zx manufacturer id 2,4 vil vil vih vil vil vid c2h high z vil device id 2,4 vil vil vih vih vil vid f7h high z vil write 1,3 vil vih vil x x x din high z vil/vih mode notes ce oe we a0 a1 a9 q0-q7 q8-q14 q15/a-1 read 1 vil vil vih x x x dout dout dout output disable 1 vil vih vih x x x high z high z highz standby 1 vih x x x x x high z high z highz deep power-down 1 x x x x x x high z high z highz manufacturer id 2,4 vil vil vih vil vil vid c2h 00h 0b device id 2,4 vil vil vih vih vil vid f7h 00h 0b write 1,3 vil vih vil x x x din din din table 2.1 bus operations for word-wide mode (byte = vih) table2.2 bus operations for byte-wide mode (byte = vil) bus operation flash memory reads, erases and writes in-system via the local cpu . all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. notes : 1.x can be vih or vil for address or control pins. 2. a0 and a1 at vil provide manufacturer id codes. a0 at vih and a1 at vil provide device id codes. a0 at vil, a1 at vih and w ith appropriate sector addresses provide sector protect code.(refer to table 4) 3. commands for different erase operations, data program operations or sector protect operations can only be successfully compl eted through proper command sequence. 4. vid = 11.5v- 12.5v. 5. q15/a-1 = vil, q0 - q7 =d0-d7 out . q15/a-1 = vih, q0 - q7 = d8 -d15 out.
6 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 command read/ silicon page/byte chip sector erase erase read clear sequence reset id read program erase erase suspend resume status reg. status reg. bus write 4 4 4 6 6 3 3 4 3 cycles req'd first bus addr 5555h 5555h 5555h 5555h 5555h 5555h 5555h 5555h 5555h write cycle data aah aah aah aah aah aah aah aah aah second bus addr 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah write cycle data 55h 55h 55h 55h 55h 55h 55h 55h 55h third bus addr 5555h 5555h 5555h 5555h 5555h 5555h 5555h 5555h 5555h write cycle data f0h 90h a0h 80h 80h b0h d0h 70h 50h fourth bus addr ra 00h/01h pa 5555h 5555h x read/write cycle data rd c2h/f7h pd aah aah srd fifth bus addr 2aaah 2aaah write cycle data 55h 55h sixth bus addr 5555h sa write cycle data 10h 30h write operations commands are written to the command interface register (cir) using standard microprocessor write timings. the cir serves as the interface between the microprocessor and the internal chip operation. the cir can decipher read array, read silicon id, erase and program command. in the event of a read command, the cir simply points the read path at either the array or the silicon id, depending on the specific read command given. for a program or erase cycle, the cir informs the write state machine that a program or erase has been requested. during a program cycle, the write state machine will control the program sequences and the cir will only respond to status reads. during a sector/chip erase cycle, the cir will respond to status reads and erase suspend. after the write state machine has completed its task, it will allow the cir to respond to its full command set. the cir stays at read status register mode until the microprocessor issues another valid command sequence. device operations are selected by writing commands into the cir. table 3 below defines 16 mbit flash family command. table 3. command definitions
7 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 command sector sector verify sector sleep abort sequence protection unprotect protect . bus write 6 6 4 3 3 cycles req'd first bus addr 5555h 5555h 5555h 5555h 5555h write cycle data aah aah aah aah aah second bus addr 2aaah 2aaah 2aaah 2aaah 2aaah write cycle data 55h 55h 55h 55h 55h third bus addr 5555h 5555h 5555h 5555h 5555h write cycle data 60h 60h 90h c0h e0h fourth bus addr 5555h 5555h * read/write cycle data aah aah c2h* fifth bus addr 2aaah 2aaah write cycle data 55h 55h sixth bus addr sa** sa** write cycle data 20h 40h notes: 1.address bit a15 -- a19 = x = don't care for all address commands except for program address(pa) and sector address(sa). 5555h and 2aaah address command codes stand for hex number starting from a0 to a14. 2. bus operations are defined in table 2. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a16 -- a19 will uniquely select any sector. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we. srd = data read from status register. 5. only q0-q7 command data is taken, q8-q15 = don't care. * refer to table 4, figure 12. ** only the top and the bottom sectors have protect- bit feature. sa = (a19,a18,a17,a16) = 0000b or 1111b is valid. command definitions(continue table 3.)
8 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force vid (11.5v~12.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from vil to vih. all addresses are don't cares except a0 and a1. the manufacturer and device codes may also be read via the command register, for instances when the MX29F1611 is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 3. byte 0 (a0=vil) represents the manfacturer's code (mxic=c2h) and byte 1 (a0=vih) the device identifier code (MX29F1611=f7h). to terminate the operation, it is necessary to write the read/reset command sequence into the cir. table 4. MX29F1611 silion id codes and verify sector protect code type a 19 a 18 a 17 a 16 a 1 a 0 code(hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer code x x x x vil vil c2h* 1 1 0 0 0 0 1 0 MX29F1611 device code x x x x vil vih f7h* 1 1 1 1 0 1 1 1 verify sector protect sector address*** vih vil c2h** 1 1 0 0 0 0 1 0 * MX29F1611 manufacturer code = c2h, device code = f7h when byte = vil MX29F1611 manufacturer code = 00c2h, device code = 00f7h when byte = vih ** outputs c2h at protected sector address, 00h at unprotected scetor address. ***only the top and the bottom sectors have protect-bit feature. sector address = (a19, a18,a17,a16) = 0000b or 1111b
9 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the cir contents are altered by a valid command sequence. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. the MX29F1611 is accessed like an eprom. when ce and oe are low and we is high the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual line control gives designers flexibility in preventing bus contention. note that the read/reset command is not valid when program or erase is in progress. read/reset command any attempt to write to the device without the three-cycle command sequence will not start the internal write state machine(wsm), no data will be written to the device. after three-cycle command sequence is given, a byte(word) load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below. byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. a byte load(word load) is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. either byte-wide load or word-wide load is determined(byte = vil or vih is latched) on the falling edge of the we(or ce) during the 3rd command write cycle. byte-wide load/word-wide load program any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. the device is programmed on a page basis. if a byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. any byte(word) that is not loaded during the programming of its page will be still in the erased state (i.e. ffh). once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data byte(word) has been loaded into the device, successive bytes(words) are entered in the same manner. each new byte(word) to be programmed must have its high to low transition on we (or ce) within 30us of the low to high transition of we (or ce) of the preceding byte(word). a6 to a19 specify the page address, i.e., the device is page-aligned on 128 page read the MX29F1611 offers fast page mode read feature. the users can take the access time advantage if keeping ce, oe at low and the same page address (a3~a19 unchanged). please refer to figure 5-2 for detailed timing waveform. the system performance could be enhanced by initiating 1 normal read and 7 fast page reads(for word mode a0~a2) or 15 fast page reads(for byte mode altering a-1~a2). page program to initiate page program mode, a three-cycle command sequence is required. there are two " unlock" write cycles. these are followed by writing the page program command-a0h.
10 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 bytes(64 words)boundary. the page address must be valid during each high to low transition of we or ce. a-1 to a5 specify the byte address within the page, a0 to a5 specify the word address withih the page. the byte(word) may be loaded in any order; sequential loading is not required. if a high to low transition of ce or we is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. the auto page program terminates when status on dq7 is '1' at which time the device stays at read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 1,7,8) sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command-80h. two more "unlock" write cycles are then followed by the sector erase command-30h. the sector address is latched on the falling edge of we, while the command (data) is latched on the rising edge of we. sector erase does not require the user to program the device prior to erase. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins on the rising edge of the last we pulse in the command sequence and terminates when the status on dq7 is "1" at which time the device stays at read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 3,4,7,9)) sector erase erase suspend this command only has meaning while the the wsm is executing sector or chip erase operation, and therefore will only be responded to during sector or chip erase operation. after this command has been executed, the cir will initiate the wsm to suspend erase operations, and then return to read status register mode. the wsm will set the dq6 bit to a "1". once the wsm has reached the suspend state,the wsm will set the dq7 bit to a "1", at this time, wsm allows the cir to respond to the read array, read status register, abort and erase resume commands only. in this mode, the cir will not resopnd to any other comands. the wsm will continue to run, idling in the suspend state, regardless of the state of all input control pins. a19 a18 a17 a16 address range[a19, -1] sa0 0 0 0 0 000000h--01ffffh sa1 0 0 0 1 020000h--03ffffh sa2 0 0 1 0 040000h--05ffffh sa3 0 0 1 1 060000h--07ffffh sa4 0 1 0 0 080000h--09ffffh ... .... ... ... ................ sa15 1 1 1 1 1e0000h--1fffffh table 5. MX29F1611 sector address table (byte-wide mode) chip erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command-80h. two more "unlock" write cycles are then followed by the chip erase command-10h. chip erase does not require the user to program the device prior to erase. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the status on dq7 is "1" at which time the device stays at read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 2,7,9) erase resume this command will cause the cir to clear the suspend state and set the dq6 to a '0', but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions.
11 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 clear status register the eraes fail status bit (dq5) and program fail status bit (dq4) are set by the write state machine, and can only be reset by the system software. these bits can indicate various failure conditions(see table 6). by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). the status register may then be read to determine if an error occurred during that programming or erasure series. this adds flexibility to the way the device may be programmed or erased. additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. the program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. to clear the status register, the clear status register command is written to the cir. then, any other command may be issued to the cir. note again that before a read cycle can be initiated, a read command must be written to the cir to specify whether the read data is to come from the array, status register or silicon id. read status register the mxic's16 mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the cir. after writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the cir. a read array command must be written to the cir to return to the read array mode. the status register bits are output on dq2 - dq7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the MX29F1611. in the word-wide mode the upper byte, dq(8:15) is set to 00h during a read status command. in the byte-wide mode, dq(8:14) are tri-stated and dq15/a-1 retains the low order address function. dq0-dq1 is set to 0h in either x8 or x16 mode. it should be noted that the contents of the status register are latched on the falling edge of oe or ce whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce or oe must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. the status register is the interface between the microprocessor and the write state machine (wsm). when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. the wsm sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. if erase fail or program fail status bit is detected, the status register is not cleared until the clear status register command is written. the MX29F1611 automatically outputs status register data when read after chip erase, sector erase, page program or read status command write cycle. the default state of the status register after powerup and return from deep power-down mode is (dq7, dq6, dq5, dq4) = 1000b. dq3 = 0 or 1 depends on sector-protect status, can not be changed by clear status register command or write state machine. dq2 = 0 or 1 depends on sleep status, during sleep mode or abort mode dq2 is set to "1"; dq2 is reset to "0" by read array command.
12 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 table 6. MX29F1611 status register notes: -1. dq7 : write state machine status 1 = ready, 0 = busy dq6 : erase suspend status 1 = suspend, 0 = no suspend dq5 : erase fail status 1 = fail in erase, 0 = successful erase dq4 : program fail status 1 = fail in program, 0 = successful program dq3 : sector-protect status 1 = sector 0 or/and 15 protected 0 = none of sector protected dq2 : sleep status 1 = device in sleep status 0 = device not in sleep status dq1 - 0 = reserved for future enhancements. these bits are reserved for future use ; mask them out when polling the status register. 2. program status is for the status during page programming or sector unprotect mode. 3. erase status is for the status during sector/chip erase or sector protection mode. 4. suspend status is for both sector and chip erase mode . 5. fail status bit(dq4 or dq5) is provided during page program or sector/chip erase modes respectively. 6. dq3 = 0 or1 depends on sector-protect status. 7. dq2 = 0 or 1 depends on whether device is in the sleep mode or not . * once in the sleep mode, dq2 is set to "1", and is reset by read array command only.- status notes dq7 dq6 dq5 dq4 dq3 dq2 in progress program 1,2, 6,7 0 0 0 0 0/1 0/1 erase 1,3, 6,7 0 0 0 0 0/1 0/1 suspend (not complete) 1,4, 6,7 0 1 0 0 0/1 0/1 (complete) 1 1 0 0 0/1 0/1 complete program 1,2, 6,7 1 0 0 0 0/1 0/1 erase 1,3, 6,7 1 0 0 0 0/1 0/1 fail program 1,5, 6,7 1 0 0 1 0/1 0/1 erase 1,5, 6,7 1 0 1 0 0/1 0/1 after clearing status register 6,7 1 0 0 0 0/1 *
13 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 five write command cycles in activating sector protection mode followed by the unprotect sector command - 40h, the automatic unprotect operation begins on the rising edge of the last we pulse in the command sequence and terminates when the status on dq7 is '1' at which time the device stays at the read status register mode.(refer to table 3,6 and figure 11,12) the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence. either protect or unprotect sector mode is accomplished by keeping wp high, i.e. protect-bit status can only be changed with a valid command sequence and wp at high. when wp is high, all sectors can be programmed or erased regardless of the state of the protect-bits. protect- bit status will not be changed during chip/sector erase operations. with wp at vil, only unprotected sectors can be programmed or erased. hardware sector protection the MX29F1611 features sector protection. this feature will disable both program and erase operations in either the top or the bottom sector (0 or 15). the sector protection feature is enabled using system software by the user(refer to table 3). the device is shipped with both sectors unprotected. alternatively, mxic may protect sectors in the factory prior to shipping the device. sector protection to activate this mode, a six-bus cycle operation is required. there are two 'unlock' write cycles. these are followed by writing the 'set-up' command. two more 'unlock' write cycles are then followed by the lock sector command - 20h. sector address is latched on the falling edge of ce or we of the sixth cycle of the command sequence. the automatic lock operation begins on the rising edge of the last we pulse in the command sequence and terminates when the status on dq7 is '1' at which time the device stays at the read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence (refer to table 3,6 and figure 10,12 ). verify sector protect to verify the protect status of the top and the bottom sector, operation is initiated by writing silicon id read command into the command register. following the command write, a read cycle from address xxx0h retrieves the manufacturer code of c2h. a read cycle from xxx1h returns the device code f7h. a read cycle from appropriate address returns information as to which sectors are protected. to terminate the operation, it is necessary to write the read/reset command sequence into the cir. (refer to table 3,4 and figure 12) a few retries are required if protect status can not be verified successfully after each operation. sector unprotect it is also possible to unprotect the sector , same as the first sleep mode the MX29F1611 features two software controlled low- power modes : sleep and abort modes. sleep mode is allowed during any current operations except that once suspend command is issued, sleep command is ignored. abort mode is excuted only during page program and chip/sector erase mode. to activate sleep mode, a three-bus cycle operation is required. the c0h command (refer to table 3) puts the device in the sleep mode. once in the sleep mode and with cmos input level applied, the current of the device is 100ua. the sleep command allows the device to complete current operations before going into sleep mode. once current operation is done, device stays at read status register mode. the status registers are not reset during sleep command. program or erase fail bit may have been set if during program/erase mode the device retry exceeds maximum count. during sleep mode, the status registers, silicon id codes remain valid and can still be read. the device sleep status bit - dq2 will indicate that the device in the sleep mode. writing the read array command wakes up the device out of sleep mode. dq2 is reset to "0" and device returns to standby current level.
14 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 abort mode to activate abort mode, a three-bus cycle operation is required. the e0h command (refer to table 3) only stops page program or sector /chip erase operation currently in progress and puts the device in sleep mode. but unlike the sleep command, the program or erase operation will not be completed. since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (dq4) or erase fail (dq5)bit will be set. after the abort command is executed and with cmos input level applied, the device current is reduced to the same level as in sleep modes. during abort mode, the status registers, silicon id codes remain valid and can still be read. the device sleep status bit - dq2 will indicate that the device in the sleep mode. similar to the sleep mode, a read array command must be written to bring the device out of the abort state without incurring any wake up latency. note that once device is waken up, clear status register mode is required before a program or erase operation can be executed. data protection the MX29F1611 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read array mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transitions or system noise. low vcc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for vcc less than vlko(= 3.2v , typically 3.5v). if vcc < vlko, the command register is disabled and all internal program/ erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the vcc level is greater than vlko. it is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when vcc is above vlko. write pulse "glitch" protection noise pulses of less than 10ns (typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil,ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one.
15 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 1. automatic page program flow chart start write data a0h address 5555h no write data 55h address 2aaah write data aah address 5555h loading end? page program completed yes yes no sr7 = 1 ? wait 100us read status register write program data/address sr4 = 0 ? program error yes no yes to continue other operations, do clear s.r. mode first program another page? operation done, device stays at read s.r. mode note : s.r. stands for status register no
16 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 2. automatic chip erase flow chart start write data 80h address 5555h no write data 55h address 2aaah write data aah address 5555h chip erase completed yes yes no sr7 = 1 ? read status register sr5 = 0 ? erase error write data aah address 5555h write data 55h address 2aaah write data 10h address 5555h erase suspend flow (figure 4.) to execute suspend mode ? yes no operation done, device stays at read s.r. mode to continue other operations, do clear s.r. mode first
17 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 3. automatic sector erase flow chart start write data 80h address 5555h no write data 55h address 2aaah write data aah address 5555h sector erase completed yes yes no sr7 = 1 ? read status register sr5 = 0 ? erase error write data aah address 5555h write data 55h address 2aaah write data 30h sector address erase suspend flow (figure 4.) to execute suspend erase ? yes no operation done, device stays at read s.r. mode to continue other operations, do clear s.r. mode first
18 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 4. erase suspend/erase resume flow chart start write data b0h address 5555h no write data 55h address 2aaah write data aah address 5555h erase has completed yes yes no sr7 = 1 ? read status register sr6 = 1 ? erase error write data aah address 5555h write data 55h address 2aaah write data f0h address 5555h yes no sr5 = 0 ? write data d0h address 5555h write data 55h address 2aaah write data aah address 5555h yes no reading end ? read array continue erase to continue other operations, do clear s.r. mode first operation done, device stays at read s,r, mode erase suspend
19 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 rating value ambient operating temperature 0 c to 70 c storage temperature -65 c to 125 c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 -0.5v to 13.5v absolute maximum ratings electrical specifications notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 14 pf vin = 0v cout output capacitance 16 pf vout = 0v switching test circuits switching test waveforms device under test diodes = in3064 or equivalent cl = 100 pf including jig capacitance 6.2k ohm 1.8k ohm +5v cl 2.0v vcc 0 v 0.8v test points input 2.0v 0.8v output ac testing: inputs are driven at vcc for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 10ns.
20 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 symbol parameter notes min. typ. max. units test conditions iil input load 1 10 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 10 ua vcc = vcc max current vin = vcc or gnd isb1 vcc standby 1 50 100 ua vcc = vcc max current(cmos) ce = vcc 0.2v icc1 vcc read 1 80 120 ma vcc = vcc max current cmos: ce = gnd 0.2v byte = gnd 0.2v or vcc 0.2v inputs = gnd 0.2v or vcc 0.2v f = 10mhz, iout = 0 ma icc2 vcc read 1 60 100 ma vcc = vcc max, current cmos: ce = gnd 0.2v byte = vcc 0.2v or gnd 0.2v inputs = gnd 0.2v or vcc 0.2v ttl: ce = vil, byte = vih or vil inputs = vil or vih, f = 5mhz, iout = 0ma icc3 vcc erase 1,2 5 10 ma ce = vih suspend current block erase suspended icc4 vcc program 1 30 50 ma program in progress current icc5 vcc erase current 1 30 50 ma erase in progress vil input low voltage 3 -0.3 0.1 v vih input high voltage 4 4.0 vcc+0.3 v vol output low voltage 0.45 v iol = 2.1ma voh output high voltage 2.4 v ioh = -400ua dc characteristics = 0 c to 70 c, vcc = 5v 5% notes: 1. all currents are in rms unless otherwise noted. typical values at vcc = 5.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. icc3 is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum o f icc3 and icc1/2. 3. vil min. = -1.0v for pulse width is equal to or less than 50ns. vil min. = -2.0v for pulse width is equal to or less than 20ns. 4. vih max. = vcc + 1.5v for pulse width is equal to or less than 20ns. if vih is over the specified maximum value, read opera tion cannot be guaranteed.
21 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 29f1611-10 29f1611-12 29f1611-15 symbol descriptions min. max. min. max. min. max. unit conditions tacc address to output delay 100 120 150 ns ce=oe=vil tpa page mode access time 50 60 70 ns ce= oe = vil tce ce to output delay 100 120 150 ns oe=vil toe oe to output delay 55 60 70 ns ce=vil tdf oe high to output delay 0 55 0 55 0 55 ns ce=vil toh address to output hold 0 0 0 ns ce=oe=vil tbacc byte to output delay 100 120 150 ns ce= oe=vil tbhz byte low to output in high z 55 55 70 ns ce=vil ac characteristics read operations test conditions: ? input pulse levels: 0v/vcc ? input rise and fall times: 10ns ? output load: 1ttl gate+100pf(including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
22 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 5-1. normal read timing waveforms addresses tacc tce tdf toh toe addresses stable data out valid vcc 5.0v gnd data out ce oe power-up standby device and address selection outputs enabled data valid standby power-down vcc we vih vil vih vil vih vil vih vil voh vol high z high z vcc 1. for real world application, byte pin should be either static high(word mode) or static low(byte mode); dynamic switching of byte pin is not recommended. note:
23 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 6. byte timing waveforms figure 5-2. page read timing waveforms addresses tacc tce tdf toh data output toe addresses stable data(dq0-dq7) ce oe byte vih vil vih vil vih vil vih vil voh vol voh vol high z high z data output data output high z tbacc high z tbhz data(dq8-dq15) tdf tpa tpa tpa valid address tacc toe* toh ce a0~a2(word mode) a-1~a2(byte mode) a3~a19 oe data out
24 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 29f1611-10 29f1611-12 29f1611-15 symbol description min. max. min. max. min. max. unit twc write cycle time 100 120 150 ns tas address setup time 0 0 0 ns tah address hold time 45 50 60 ns tds data setup time 45 50 60 ns tdh data hold time 10 10 10 ns toes output enable setup time 0 0 0 ns tces ce setup time 0 0 0 ns tghwl read recover timebefore write 0 0 0 tcs ce setup time 0 0 0 ns tch ce hold time 0 0 0 ns twp write pulse width 45 50 60 ns twph write pulse width high 50 50 50 ns tbalc byte(word) address load cycle 0.3 30 0.3 30 0.3 30 us tbal byte(word) address load time 100 100 100 us tsra status register access time 100 120 150 ns tcesr ce setup before s.r. read 100 100 100 ns tvcs vcc setup time 2 2 2 us ac characteristics write/erase/program operations
25 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 7. command write timing waveforms tas toes tds tah din tdh tch tghwl valid addresses ce oe data high z we (d/q) vcc tcs twph twp twc tvcs 1. byte pin is treated as address pin all timing specifications for byte pin are the same as those for address pin. note: 2. byte pin is sampled on the falling edge of we or ce during the 3rd command write bus cycle; for real world application, byte pin should be either static high(word mode) or static low(byte mode).
26 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 8. automatic page program timing waveforms tas tds tah tdh tbalc a15~a19 ce oe data we twph twp twc aah 55h a0h srd 55h 55h aah 2ah 55h 55h word offset address page address page address a6~a14 a0~a5 tbal tces tsra write data note: low/high byte select a-1 (byte mode only) 1.please refer to page 9 for detail page program operation. last low/high byte select last word offset address last write data
27 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 9. automatic sector/chip erase timing waveforms tas tds tah tdh a16~a19 ce# oe data we twph twp twc aah 55h 80h srd 5555h 2aaah 5555h sa/* a15 a0~a14 tcesr tces tsra notes: 5555h 2aaah */5555h aah 55h 30h/10h 1."*" means "don't care" in this diagram. 2."sa" means "sector adddress".
28 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 10. sector protection algorithm start, plscnt=0 write data 60h address 5555h no write data 55h address 2aaah write data aah address 5555h increment plscnt, to protect sector again yes yes no sr7 = 1 ? read status register to verify protect status ? data = c2h ? write data aah address 5555h write data 55h address 2aaah write data 20h, sector address* verify protect status flow (figure 12) device failed yes no protect sector operation terminated sector protected,operation done, device stays at verify sector protect mode device stays at read s.r. mode yes plscnt = 25 ? no note : *only the top or the bottom sector address is vaild in this feature. i.e. sector address = (a19,a18,a17,a16) = 0000b or 1111b
29 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 11. sector unprotect algorithm start, plscnt=0 write data 60h address 5555h no write data 55h address 2aaah write data aah address 5555h increment plscnt, to unprotect sector again yes yes no sr7 = 1 ? read status register to verify protect status ? data = 00h ? write data aah address 5555h write data 55h address 2aaah write data 40h, sector address* verify protect status flow (figure 12) device failed yes no unprotect sector operation terminated sector unprotected,operation done, device stays at verify sector protect mode device stays at read s.r. mode yes plscnt = 25 ? no note : *only the top or the bottom sector address is vaild in this feature. i.e. sector address = (a19,a18,a17,a16) = 0000b or 1111b
30 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 12. verify sector protect flow chart start write data 90h, address 5555h write data 55h, address 2aaah write data aah, address 5555h ptoect status read* * 1. protect status: data outputs c2h as protected sector verified code. data outputs 00h as unprotected sector verified code. 2. sepecified address will be either (a19,a18,a17,a16,a1,a0) = (000010) or (111110), the rest of the address pins are don't care. 3. silicon id and test row lock status can be read via this flow chart. refer to table 4.
31 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 13. command write timing waveforms(alternate ce controlled) tas toes tds tah din tdh twh tghwl valid addresses ce oe data high z we (d/q) vcc tws tcph tcp twc tvcs note: 1. byte pin is treated as address pin. all timing specifications for byte pin are the same as those for address pin. 2. byte pin is sampled on the falling edge of we or ce during the 3rd command write bus cycle; for real world applicaton, byte oin should be either static high(word mode) or static low(byte mode).
32 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 figure 14. automatic page program timing waveform(alternate ce controlled) tas tds tah tdh tbalc a15~a19 ce(1) oe data we tcph tcp twc aah 55h a0h srd 55h 55h aah 2ah 55h 55h word offset address page address page address a6~a14 a0~a5 tbal tces tsra write data note: low/high byte select a-1 ((byte mode only) 1.please refer to page 9 for detail page program operation. last word offset address last low/high byte select last write data
33 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 limits parameter min. typ. max. (note 1) units chip/sector erase time 100 (note 2) ms page programming time 5 (note 3) ms chip programming time 80 150 sec erase/program cycles 10,000 cycles byte program time 39 us erase and programming performance min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. latchup characteristics *note 1: max values are all evaluated with polling the status in stead of internal state machine time out. *note 2: the ic internal state machine is set 2000 ms as maximum chip/sector erase time out. *note 3: we set 60 ms as production test condition, whereas, the ic internal state machine is set 150 ms as maximum programming time out.
34 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 44-pin plastic sop item millimeters inches a 28.70 max. 1.130 max. b 1.10 [ref] .043 [ref] c 1.27 [tp] .050 [tp] d .40 .10 [typ.] .016 .004 [typ.] e .010 min. .004 min. f 3.00 max. .118 max. g 2.80 .13 .110 .005 h 16.04 .30 .631 .012 i 12.60 .496 j 1.72 .068 k .15 .10 [typ.] .006 .004 [typ.] l .80 .20 .031 .008 note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. 122 23 44 a dc b e gf h i j k l
35 p/n: pm0440 rev. 1.6, jul. 16, 1998 MX29F1611 revision history rev. # description date 1.1 write-erase cycles change from 1,000/10,000 to 100,000. 10/29/1997 1.2 programming performance table updated again 03/19/1998 1.3 write-erase cycles change from 100,000 to 10,000 04/09/1998 1.4 correct page programming waveform and delete ry/by,pwd wafewaves on page 26 & 04/10/1998 page 32 respetively 1.5 vil max. 0.1-->0.4 ; vih min. 4-->3.5 07/13/1998 1.6 vil max. 0.4-->0.1 ; vih min. 3.5-->4 07/16/1998
36 MX29F1611 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice.

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